Individual semiconductor devices in integrated circuits are interconnected by means of one or more patterned conductive layers overlying the semiconductor devices. It is particularly advantageous to provide a plurality of patterned conductive layers separated from one another and from the underlying semiconductor devices by a layer of insulating material. This practice permits a higher density of interconnections per unit area than can be provided by a single patterned conductive layer, and simplifies design by permitting interconnection paths implemented in one conductive layer to cross over interconnection paths implemented in other conductive layers.
Multilevel interconnection structures are made by alternately depositing and patterning layers of conducting material, typically aluminum alloys such as Al-Si, and layers of insulating material, typically SiO.sub.2. The patterning of underlying layers defines a nonplanar topography which complicates reliable formation of overlying layers. In particular, the nonplanar topography of underlying conductive layers is replicated in overlying insulating layers to provide vertical steps in the insulating layers. Moreover, small holes are formed in the insulating layers to permit interconnection to underlying conductive layers or device contacts.
The subsequent formation of a conductive layers overlying the nonplanar topography of the insulating layers is complicated by thinning of the conductive layers at the tops of the steps, cusping or microcracking of the conductive layers at the bottoms of the steps, and formation of voids in the conductive layers in small via and contact holes. Moreover, uneven formation of the conductive layers reduces the resistance of the patterned conductive material to electromigration, reducing the reliability of the completed integrated circuit.
Patterning of the resulting conductive layers may also be complicated by the nonplanar topography. For example, conductive material at the bottom of steps is difficult to remove and may provide unwanted conductive paths between adjacent regions of a conductive layer.
The formation of further insulating layers is also complicated by the nonplanar topography of the conducting layers. Weaknesses are present in the insulating layers at the tops and bottoms of steps. Cracks form at such weaknesses, providing unwanted conductive paths between adjacent conductive layers.
The Resist Etch Back (REB) technique is frequently used to modify the nonplanar topography of insulating layers in an effort to minimize or avoid the above problems. In the REB technique, a thick layer of photoresist is formed on a nonplanar insulating layer and the photoresist is etched back until peaks or steps in the insulating layer topography are exposed, but valleys or troughs in the insulating layer topography are filled with remaining photoresist. The etching process is then controlled so that the etch rate of the insulating layer is substantially equal to the etch rate of the photoresist. Peaks or steps in the insulating layer topography are etched while valleys or troughs are protected by the photoresist, so the height of the peaks or steps is reduced.
While the REB technique reduces the height of peaks or steps in the insulating layer topography, it does not necessarly eliminate the sharp edges or vertical sidewalls of steps. These sharp edges and vertical sidewalls cause many of the problems referred to above, and such problems persist when the REB technique is used.
The REB technique is also subject to macroloading and microloading effects which can have a considerable impact on the results obtained in a production environment. The macroloading effect is a run to run or wafer to wafer variation of the relative etch rates of the insulating material and photoresist. Because the etch rates must be substantially equal to obtain an optimum reduction in step height, such variations cause a reduction in step height which is less than optimum. In severe cases, macroloading effects may actually accentuate deviations from a planar topography.
The microloading effect is enhanced localized etching of the photoresist in narrow valleys or troughs and at the edges of steps in the insulating layer. Microloading is primarily due to oxygen species liberated during etching of the insulating layer defining the side walls of the valleys, troughs or steps. The enhanced localized etching causes formation of sharp notches or trenches which in turn cause the problems referred to above.
The sharp edges and vertical side walls of steps and notches or trenches in the insulating layers can be avoided by ion milling the insulating layers in a low pressure inert gas plasma, typically an argon plasma. Because sputter ejection is favoured for ions which arrive at a specific angle to the surface of the insulating layer, the side walls of steps and notches or trenches are tapered at an angle corresponding to the favoured angle, and sharp edges are avoided in the resulting insulating layer topography.
While argon facetting techniques avoid sharp edges and vertical side walls in the insulating layers, they do not substantially reduce the height of steps and peaks in the insulating layer topography. Hence some of the patterning problems referred to above persist when argon facetting techniques are used.